Datasheet: 9e102

Not recommended. The 9E102 is designed for 5V TTL. At 3.3V, delays increase unpredictably, and outputs may not reach valid logic levels. Use a level shifter or choose a modern 3.3V delay line (e.g., 74LVC1GXX series).

| Symptom | Possible Cause | Solution | |---------|----------------|----------| | No output signal | Missing Vcc or GND | Verify power pins (Pin 8 = +5V, Pin 3 = GND) | | Output stuck HIGH/LOW | Damaged input stage | Test input with oscilloscope; replace IC | | Wrong delay time | Wrong temperature, Vcc drift | Check Vcc tolerance (4.75–5.25V); use temp-stable supply | | Jitter on output | Power supply noise | Add 0.1 µF + 10 µF bypass caps | | Output truncated | Input pulse shorter than delay | Ensure input pulse width > 120 ns for reliable transfer | If the original 9E102 is obsolete or unavailable, consider these alternatives: 9e102 datasheet

Always verify pin compatibility, voltage levels, and timing tolerances before substituting. Q1: Is the 9E102 a standard logic gate? No. It is a delay line —a specialized IC that propagates a logic signal with a fixed time shift. It does not perform Boolean logic. Not recommended